Welcome to IEEE TCCA Email-Monthly, Feb. 2005. 1. New papers published online by Computer Architecture Letters *Website: *Submitted by: Kevin Skadron 2. TACS: Second Workshop on Temperature Aware Computer Systems *June 5, 2005, Madison, WI *Submission deadline: Late March, 2005 *Kevin Skadron *http://www.cs.virginia.edu/~skadron/tacs05 3. ANCHOR 2005: Advanced Networking and Communications Hardware Workshop *Madison, Wisconsin, June 4-8 2005 *SUBMISSION DEADLINE: April 1st, 2005 *Submitted by: Gokhan Memik *CALL FOR PAPERS http://www.ece.northwestern.edu/anchor 4. WDDD'05: Workshop on Duplicating, Deconstructing, and Debunking *June 4, 2005, Held in conjunction with ISCA-32 Madison, Wisconsin *Submissions due: April 22, 2005, (Abstractse: April 15, 2005) *Submitted by: Trey Cain *CALL FOR PAPERS http://www.ece.wisc.edu/~wddd 5. PACRIM'05 2005 IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing *August 24-26, 2005 Victoria, BC, Canada *Submission Deadline: March 1, 2005 *Call for Papers: http://www.PacRimConf.ca *Submitted by Kin Li 6. HOT Chips 17: A Symposium on High Performance Chips *AUGUST 14-16, 2004 STANFORD UNIVERSITY, PALO ALTO, CA *Deadline for submissions: March 25, 2004 *CALL FOR PAPERS: http://www.hotchips.org *Submitted by Alan Smith 7. Workshop on Complexity-Effective Design *June 5, 2005, Madison, Wisconsin *Submission Deadline: April 25, 2005 *Submitted by Dave Albonesi 8. Workshop on Computer Architecture Education *June 5, 2005, in conjunction with ISCA-32, Madison, Wisconsin *Submission Due Date: May 6, 2005 *Submitted by Edward F Gehringer ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ New papers published online by Computer Architecture Letters Computer Architecture Letters announces our two most recent papers, which are publicly available at http://www.comp-arch-letters.org/2005paps.html. We continue to seek new submissions and remain committed to fast and accurate review. Our mean time to decision remains one month, with an acceptance rate of approximately 21%. For more information on submission and for an archive of past papers, please see http://www.comp-arch-letters.org - Y. Sazeides, R. Kumar, D. M. Tullsen, T. Constantinou. "The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best." Volume 4, Jan. 2005. - O. Mutlu, H. Kim, J. Stark, and Y. N. Patt. "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor." Volume 4, Jan. 2005. Abstracts --------- Y. Sazeides, R. Kumar, D. M. Tullsen, T. Constantinou. "The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best." Volume 4, Jan. 2005. Abstract: This paper shows that if the execution of a program is divided into distinct intervals, it is possible for one processor or configuration to provide the best power efficiency over every interval, and yet have worse overall power efficiency over the entire execution than other configurations. This unintuitive behavior is a result of a seemingly intuitive use of power efficiency metrics, and can result in suboptimal design and execution decisions. This behavior may occur when using the energy-delay product and energy-delay^2 product metrics but not with the energy metric. O. Mutlu, H. Kim, J. Stark, and Y. N. Patt. "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor." Volume 4, Jan. 2005. Abstract: Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed during runahead mode, previous approaches discarded those results instead of trying to utilize them in normal mode execution. This paper evaluates the effect of reusing the results of pre-executed instructions on performance. We find that, even with an ideal scheme, it is not worthwhile to reuse the results of pre-executed instructions. Our analysis provides insights into why result reuse does not provide significant performance improvement in runahead processors and concludes that runahead execution should be employed as a prefetching mechanism rather than a full-blown prefetching/result-reuse mechanism. ------------------------------------------------------------------------- --- Call for Papers Second Workshop on Temperature Aware Computer Systems (TACS) June 5, 2005, Madison, WI http://www.cs.virginia.edu/~skadron/tacs05 Held in conjunction with the 32nd International Symposium on Computer Architecture Many analysts suggest that increasing power density and resulting difficulties in managing on-chip temperatures are some of the most urgent obstacles to continued scaling of VLSI systems within the next five to ten years. Just as has been done before for power-aware computing, "temperature-aware" computing must be approached not just from the packaging and circuit-design communities, but also from the processor- and systems- architecture communities. There is growing interest in cooling solutions from the processor- and systems-architecture domains, as evidenced by recent work on fetch throttling, dynamic voltage scaling, and process scheduling in response to thermal stress; and some progress has been made on modeling infrastructure for this kind of research. But research so far has only scratched the surface of what is possible. This topic area presents a wide-open field for new research, with lots of "low-hanging fruit", and interesting opportunities for wide-ranging inter-disciplinary work. This workshop will serve as a forum to explore a broad spectrum of topics pertaining to temperature-aware computer systems, for researchers from multiple fields to exchange ideas and initiate collaborations, and to continue establishing temperature-aware computing as an important research topic in its own right. Conributions from all aspects of temperature-aware design are encouraged, related topics like reliability, leakage, thermal sensors, etc. We especially encourage submissions involving collaboration between architects and thermal engineers! In fact, the goal of this workshop is to stimulate the widest possible collaboration among architects and other engineers on topics related to temperature-aware design. This is the second year of the TACS workshop. Last year's TACS, held in conjunction with ISCA-31, was extremely successful, with good attendance, four strong papers covering diverse topics, an exciting keynote speech by Luiz Barroso of Google, and a vigorous panel discussion. Submissions are welcomed on any topic pertaining to temperature-aware architecture, including but not limited to: * Modeling and validation * Thermal implications of novel architectures, design styles, or technologies * Dynamic thermal management for the CPU, CMPs, SoCs, other system components, clusters, data centers, etc. * Circuit/architecture/OS cooperation * Scheduling techniques * Sensitivity of other metrics to operating temperature * Application-specific thermal optimizations * New benchmark applications and sampling techniques for thermal studies * Workload characterization * Interaction of thermal management, energy efficiency (especially leakage), and voltage stability * Interaction of thermal management and other runtime optimizations * All architecture-related aspects of temperature-dependent reliability effects * Interaction of thermal management with real-time requirements * Interaction of manufacturing, packaging, and cooling with architecture * Architecture impacts of novel cooling techniques (from chip-level to data-center level) * New thermal-sensor architectures The paper should be in IEEE conference format and at most ten pages in length including all figures, references, etc. Excessively long papers will be rejected without review. Submission deadline: Late March, 2005 Author notification: TBD Final manuscripts: TBD ------------------------------------------------------------------------- Advanced Networking and Communications Hardware Workshop (ANCHOR) http://www.ece.northwestern.edu/anchor The rapid expansion of networking applications and data traffic are leading to new specialized network component designs that would keep up with the growing field of networking and communications. Network component design becomes more challenging as the performance and usage of communication networks increase. This workshop focuses on the architectural design approaches for packet-switched networks. From sensor to storage area networks, packet-switched networks are utilized in a wide range of system domains. Furthermore, the workshop aims at providing a forum for scientists and engineers from academia and industry to discuss their latest research on emerging network services. There is a growing interest in extensible networks, overlay networks, and grid computing. Higher layer processing built in hardware can powerfully support these networks and computational styles. This year^?s workshop will be looking for contributions that will benefit these communities. Topics of particular interest include, but are not limited to: * Switch and router architectures (including optical and fiber channel networks) * Communications and network processors * Co-processors (classification, search engine, traffic manager, etc) * Specialized offload engines (protocol offload engines, I/O adapters, etc.) * Architectures for security applications * Architectures for processor-memory interconnection * Hardware accelerators for emerging network services (overlay, extensible, grid computing, etc) * Application-specific designs (compression, QoS, etc.) * Power-efficient architectures * High-level software for networking hardware ------------------------------------------------------------------------- ************************************************************* CALL FOR PAPERS: WDDD 2005 ************************************************************* Workshop on Duplicating, Deconstructing, and Debunking http://www.ece.wisc.edu/~wddd Held in conjunction with ISCA-32 Madison, Wisconsin USA June 4, 2005 ------------------------------------------------------------- IMPORTANT DATES --------------- Abstracts due: April 15, 2005 Submissions due: April 22, 2005 Acceptance: May 2, 2005 Final version: May 23, 2005 WORKSHOP OVERVIEW ----------------- WDDD provides the computer systems research community a forum for work that validates or duplicates earlier results; deconstructs prior findings by providing greater, in-depth insight into causal relationships or correlations; or debunks earlier findings by describing precisely how and why proposed techniques fail where earlier successes were claimed, or succeed where failure was reported. Traditionally, computer systems conferences and workshops focus almost exclusively on novelty and performance, neglecting an abundance of interesting work that lacks one or both of these attributes. A significant part of research--in fact, the backbone of the scientific method--involves independent validation of existing work and the exploration of strange ideas that never pan out. This workshop provides a venue for disseminating such work in our community. Published validation experiments strengthen existing work, while thorough comparisons provide new dimensions and perspectives. Studies that refute or correct existing work also strengthen the research community, by ensuring that published material is technically correct and has sound assumptions. Publishing negative or strange or unexpected results will allow future researchers to learn the hard lessons of others, without repeating their effort. This workshop will set a high scientific standard for such experiments, and will require insightful analysis to justify all conclusions. The workshop will favor submissions that provide meaningful insights and point to underlying root causes for the failure or success of the technique under investigation. Acceptable work must thoroughly investigate and clearly communicate why the proposed technique performs as the results indicate. Rebuttals may be invited for debunking submissions. SUBMISSION TOPICS ----------------- * Independent validation of earlier results with meaningful analysis * In-depth analysis and sensitivity studies that provide further insight into earlier findings, or identify key parameters or assumptions that affect the results * Studies that refute earlier findings, with clear justification and explanation * Negative results for ideas that intuitively make sense and should work, along with explanations for why they do not * EXPANDED SCOPE: In addition to the topics of computer architecture and microarchitecture that have previously been the focus of WDDD, this year's workshop is being expanded to include papers in the related areas of code generation and optimization, including efficient profiling mechanisms, static and dynamic optimization, feedback driven and adaptive optimization, and modulo/trace scheduling. SUBMISSION GUIDELINES --------------------- * Submit a 200-word abstract plus title and list of authors in plain text email by April 15 to tcain@us.ibm.com. * Submit a 5000-word or less (brief and to-the-point submissions are strongly encouraged) double-spaced manuscript by April 22 as a PS or PDF file on the workshop website www.ece.wisc.edu/~wddd Inappropriate submissions, as described in the submitted abstract, will be rejected outright. Similarly, inflammatory, abusive, or overtly combative and negative submissions will not be considered. Accepted papers will be published in the ISCA-32 workshop proceedings. WORKSHOP ORGANIZERS ------------------- Bryan Black, Intel Labs, bryan.black@intel.com Harold Cain, IBM Research, tcain@us.ibm.com PROGRAM COMMITTEE ----------------- Mauricio Breternitz, Intel Brad Calder, University of California-San Diego Babak Falsafi, Carnegie-Mellon University Ken Leuh, Intel Mikko Lipasti, University of Wisconsin-Madison Ravi Nair, IBM Research Yale Patt. University of Texas-Austin Ryan Rakvic, Intel ---------------------------------------------------------------------- ---------------------------------------------------------------------- **************** CALL FOR PAPERS *************** 2005 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM'05) www.PacRimConf.ca August 24-26, 2005, Victoria, B.C., Canada Sponsored by IEEE Victoria Section Co-sponsored by the University of Victoria Established in 1987, Pacific Rim Conference is the premier IEEE biennial event in the Pacific Northwest. It is our pleasure to invite you to participate in this event. If you wish, please consider organizing a special session. The scope of PACRIM'05 encompasses but is not limited to: Mobile and Personal Communications Computer Architecture Coding, Modulation and Spread Spectrum Parallel, Distributed and Grid Computing Computer Networks Internet Applications and Web Mining Multimedia and Network Processors Neural Networks and Genetic Algorithms Computer Security Embedded Systems OFDM and MIMO Database and Knowledge-Based Systems DSP Applications in Communication Adaptive Filters and Algorithms Image and Video Processing Wavelets and Filter Banks Speech and Audio Processing Cryptography IMPORTANT DEADLINES 2000 Word Draft Paper: March 1, 2005 Notification of Acceptance/Rejection: April 1, 2005 Camera Ready Copy: May 1, 2005 Special Session Proposal Deadline: March 1, 2005 Instructions for paper submission and other important information can be found on the conference website http:\\www.PacRimConf.ca General enquires on PACRIM'05 can be addressed to either of the General Co-Chairs: Dr. Aaron Gulliver or Dr. Fayez Gebali Dept. of Electrical & Computer Engineering University of Victoria P.O. Box 3055, STN CSC Victoria, BC, V8W 3P6 Canada Fax: +1-250-721-6052 Email: agullive@ece.uvic.ca or fayez@ece.uvic.ca Accepted papers will be published in the conference proceedings and will appear on IEEE Xplore. ------------------------------------------------------------------------- ----------- CALL FOR PAPERS HOT Chips 17 - A Symposium on High Performance Chips AUGUST 14-16, 2004 STANFORD UNIVERSITY, PALO ALTO, CA AUTHOR'S SCHEDULE Deadline for submissions: March 25, 2004 Notification of acceptance: April 30, 2004 Deadline for final version: July 20, 2004 AREAS OF INTEREST: Microprocessors Systems-on-chip Embedded processors Digital signal processors Chipset Chips Application-specific processors Network/security processors Graphics/Multimedia/Game processors Communication/networking chips Wireless LAN/Wireless WAN chips Novel chips: quantum computing, micro-array Low-power chips/Dynamic Power Management Reconfigurable chips/processors Chips built from FPGAs Reliability and design for test Compiler technology Operating system/chip interaction Advanced semiconductor process technology Advanced packaging technology Performance evaluation AUTHOR INFORMATION AND FORMAT Presentations at HOT Chips are in the form of 30-minute talks. Presentation slides will be published in the HOT Chips Proceedings. Participants are not required to submit written papers, but a select group will be invited to submit a paper for inclusion in a special issue of IEEE Micro. Submissions must consist of a title, extended abstract (two pages max.), and the presenter's contact information (name, affiliation, job title, address, phone(s), fax, and email). Please indicate whether you have submitted, intend to submit, or have already presented or published a similar or overlapping submission to another conference or journal. Also indicate if you would like the submission tobe held confidential; we do our best to maintain confidentiality if requested. Submissions should be in plain ASCII text, pasted into the message; do not submit .doc files, .txt files, MIME'd email, any attachments or other formats. Submissions containing figures may be submitted in pdf, but plain ASCII text is strongly preferred. Submissions are evaluated by the Program Committee on the basis of performance of the device(s), degree of innovation, use of advanced technology, potential market significance, and anticipated interest to the audience. Research and software contributions will be evaluated with similar criteria. Please mail your submissions in plain ASCII text (in the message, not as an attachment!) by March 25, 2005 to: hotchipssubmit@atlas.cs.berkeley.edu Authors will be notified as to acceptance by April 30, 2005. Send questions relating to the program to the program chairs at: hotpcchairs@atlas.cs.berkeley.edu and questions relating to conference operation or organization to the general chair, Pradeep Dubey, at: hotchair@atlas.cs.berkeley.edu . Program Committee Co-Chairs Prof. Alan Jay Smith, Univ. of California, Berkeley John Sell, Microsoft Sponsored by the Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society Program Committee: Alan Smith - UC Berkeley John Sell - Microsoft Forest Baskett - New Enterprise Associates Keith Diefendorf - Apple Pradeep Dubey - Intel Christos Kozyrakis - Stanford Teresa Meng - Stanford Chuck Moore - AMD John Nickolls - NVidia Rakesh Patel - Altera Tom Peterson - MIPS Howard Sachs - Telairity Mitsuo Saito - Toshiba Kimming So - Broadcom Marc Tremblay - SUN John Wawryznek - UC Berkeley ------------------------------------------------------------------------- ------------------------------------------------------------------------- Workshop on Computer Architecture Education Held in conjunction with the 32nd International Symposium on Computer Architecture Madison, Wisconsin Sunday, June 5, 2005 Theme This is the twelfth in a series of workshops that have been held at both ISCA and at HPCA, most recently at ISCA 2004 in Munich. The goal of the workshop is to provide a forum for educators to discuss and share their experiences and teaching philosophy. The goal is for participants to come away from the workshop with new ideas on delivering courses in computer architecture. Topics of interest include, but are not limited to, the following. Topics of interest * New approaches to introductory courses * Advanced courses * Active learning * New curricula * National differences in curricula * Interdepartmental issues (CS/ECE) * Distance education * Industrial support for teaching * Encouraging students to do research * Encouraging students to pursue the Ph.D. * Hardware tools * Simulators and other software tools * Teaching embedded systems * Prototyping * Visualization aids * VLSI design packages * Web-based materials * Textbook development * Textbook selection * Integration of research into teaching Special Session on Embedded Systems Education A special session on Embedded Systems Education will comprise an integral part of the WCAE workshop. The goal of the special session is to bring researchers, educators, and industrial representatives together to share design, research, and education experiences in embedded systems. Topics and of interest include but are not limited to: * Embedded systems curricular design and implementation * Architectural issues specific to embedded systems * Software issues specific to embedded systems * Industrial needs regarding embedded systems education * Hardware/software co-design * Teaching embedded systems Format The special session will involve: * Presentations of accepted papers * Poster session for accepted papers * A roundtable discussion involving a panel of embedded-systems experts Submission of contributions Interested authors should submit a full paper (not to exceed 8 pages, with a minimum font size of 10 points) to Edward F. Gehringer e-mail: efg@ncsu.edu Center for Embedded Systems Research Dept. of Electrical and Computer Engineering North Carolina State University Box 7256 Raleigh, NC 27695-7256 +1 919 515-2066 Submissions to the special session should be directed to Kenneth G. Ricks e-mail: kricks@coe.eng.ua.edu Dept. of Electrical and Computer Engineering The University of Alabama 317 Houser Hall Box 870186 Tuscaloosa, Alabama 35487-0286 +1-205-348-9777 Electronic submission is required, preferably as a PDF attachment to an e-mail message. Industry Participation We encourage participation by book publishers, computer manufacturers, software vendors, or companies which develop or market products used in the delivery of computer architecture education. Any company interested in participating in the workshop should contact the organizer at the address above. Important Dates Submission Due Date: May 6, 2005 Author Notification: May 13, 2005 Final Paper Due Date: May 20, 2005 Copies of papers presented at the workshop will be made available at the workshop, and in archival form on the Web. ------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe